Thermal-aware 3D floorplanner

We introduce Direct Mapping, a new floorplanner suitable for the thermal optimization of large 3D Multiprocessor Systems-on-Chips (3D MPSoCs). Below we show an example of a thermal optimization of a Niagara architecture composed of 48 cores distributed in 4 layers:

Architecture	Layer 1	Layer 2	Layer 3	Layer 4
Original
Optimized

Background

Three-dimensional (3D) integration is widely recognized as today’s most promising alternative to provide increased performance and chip footprint reduction for multi-core processors. The performance improvement is allowed by a decreased total wiring length, and thus reduced interconnect delay times, and heterogeneous many-core integration. However, in 3D scenarios, power density increases linearly with the number of layers leading to significant thermal issues that negatively affect the reliability and lifetime of integrated circuits.

Algorithm

Direct Mapping overview

Results

For an extensive analysis of the method, please check the doctoral dissertation (pp 133-157):

Arnaldo Lucas, I. (2013). Bioinspired heuristics for the thermal-aware Floorplanning of 3D MPSoCs. Heurísticas bioinspiradas para el problema de Floorplanning 3D térmico de dispositivos MPSoCs (Doctoral dissertation, Universidad Complutense de Madrid).